1. Field of the Invention
The present invention relates to semiconductor devices and methods for testing and characterizing semiconductor devices. More particularly, the invention relates to characterization, testing, and binning of semiconductor devices such as integrated circuits.
2. Description of Related Art
Overall power consumption for semiconductor devices (e.g., semiconductor integrated circuits (ICs) such as logic or memory ICs) is a combination of dynamic (active) power consumption and static (leakage) power consumption. As devices have reduced in size and the power requirements (especially dynamic power requirements) have been reduced, static power consumption has become a more significant factor in overall power consumption for integrated circuits and semiconductor devices. Static power consumption is especially important in portable electronic devices as static (idle) power consumption directly affects battery life. Thus, the control and optimization of static power consumption is increasingly needed for the production of semiconductor devices used in portable electronic devices as well as other electronic devices.
Variations during the manufacturing of integrated circuits (e.g., variations during IC processing) may cause variation between integrated circuits that are manufactured to the same design specifications. For example, manufacturing variations such as, but not limited to, equipment variations, position on a wafer, process fluctuations, and/or operator variations may cause one or more parameters to vary between integrated circuits formed on the same wafer, integrated circuits formed in the same lot (batch), and/or integrated circuits formed on different wafers in different lots. Because of these manufacturing variations, integrated circuits with the same design may have different static power consumption characteristics. Using integrated circuits with excessive power consumption may lead to decreased battery life and/or decreased operational lifetime in electronic devices such as portable electronic devices. Thus, in order to maintain desired levels of battery life and/or operational lifetime, some integrated circuits may have to be “failed” because their static and/or dynamic power consumption is too high (e.g., power consumption that would lead to unacceptable battery life) and/or the voltage supplied to the integrated circuit may be limited to avoid excessive power consumption.
Binning of integrated circuits may be used to sort manufactured integrated circuits based on their static (or dynamic) power consumption. Post-manufacturing binning may be used to separate the manufactured integrated circuits into different bins based on worst-case static power consumption of each integrated circuit after testing of leakage currents in the integrated circuits at one or more voltage levels. Binning allows integrated circuits with higher static leakage currents to be accepted while maintaining the worst-case static power consumption at acceptable levels (e.g., by limiting the supply voltage provided to the integrated circuit). Binning the integrated circuits allows the integrated circuits to be sorted for use in selected products (e.g., selected portable electronic devices) based on the worst-case power consumption or maximum supply voltage for each bin. Binning of manufactured integrated circuits with multiple bins may produce better average power (static and/or dynamic) and better manufacturing yield, which reduces costs.
A drawback to binning is the time used to test and bin the integrated circuits after manufacturing the integrated circuits. Testing the integrated circuits at more voltages (e.g., bin voltages) requires more test time but can produce better average power and higher yield. Reducing the number of test voltages (bin voltages) to decrease test time, however, reduces average power and decreases yield. The number of bins used, therefore, may be a balance between time and desired power and/or yield. The number of bins may be reduced by tailoring the bins to more closely represent the population data.
Another drawback to most current binning schemes is that testing may be limited to a single operating frequency or a small operating frequency range. Because the integrated circuit is binned at only the single operating frequency or in the small operating frequency range, operation of the integrated circuit is limited to the single operating frequency or the small operating frequency range. Such limits in the operating frequency limits the ability of the integrated circuit (e.g., the CPU or the SoC) to be used for multiple programs or operations that require wide ranges of operating frequencies. Increasing the frequency range of the integrated circuit may be possible with further characterization (e.g., binning at other frequencies); however, further characterization increases testing time.